Multiple-character generator

ABSTRACT

A circuit for converting a single coded input character into a plurality of coded output characters by applying a portion of the coded input character to a character generator device and deriving the remaining inputs to the character generator device from a counter which is incremented each time an output character is generated. The multiple character sequence is terminated when a predetermined output is obtained from the character generator.

United States Patent [72] Inventor Stephen A.Grosky 3,413,610 11/1968Botzer 340/3241 Monroe, Conn. 3,422,420 1/1969 Clark 340/324.1 [21]Appl. No. 864,765 3,440,638 4/1969 Vaikenburg... 340/3241 [22] FiledOct.8, 1969 3,483,547 12/1969 Henderson 340/3241 [45] 1971 PrimaryExaminer-Maynard R. Wilbur [73] Ass'gnee The uunker'Ramo 9' AssistantExaminer-Jeremiah Giassman Stamford Conn Attorney-Frederick M. Arbuckle[54] MULTIPLE-CHARACTER GENERATOR 10 Claims, 2 Drawing Figs. [52] U.S.C1235/154,

340/324'1 ABSTRACT: A circuit for converting a single coded input [51]Int. Cl 0413/02 character i a l i y of coded output characters by app|y[50] Field ofSearch 235/154; ing a portion f the coded input characterto a character 3403413241 154 generator device and deriving theremaining inputs to the R f C" d character generator device from acounter which is incre- [56] e fences e mented each time an outputcharacter is generated. The multi- UNITED STATES PATENTS ple charactersequence is terminated when a predetermined 3,396,377 8/1968 Strout340/324.1 output is obtained from the charactergenerator.

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$2? 7 q ocutnnon 9 40 j o 52 52 a W 14 s so I run or seoucucz unscrew oI lust m" M l 107% an! a. I I -50 ENABLE MULTIPLE-CHARACTER GENERATORMULTIPLE CHARACTER GENERATOR This invention relates to a circuit forgenerating a plurality of coded output characters in response to thereceipt of a single input character, and more particularly to a circuitfor generating a plurality of output characters as a result of thedepression of a single key on a keyboard.

In most applications where a keyboard is being utilized to enterinformation into a data processing system, there are charactercombinations, such as words or short phrases, which frequently appear.For exampleflwords such as "buy" sell, and "cancel might appearfrequently in a sales-orientated application. Editing or otherinstruction characters, such as tab,

skip, and the like, may, in some application be included in the multiplecharacter sequences. In such applications, substantial operator time canbe saved if these words are generated as a result of a single keydepression. However, the multiple character combination required .foreach application generally differ, and even the words or other charactercombinations required within a single application may differ with time.Also, the number of characters in the sequences will vary both within asingle application and from application to application.

l-ieretofore, multiple character generation has been accomplished byhard wiring the multiple character sequences into the control logic ofthe system. Thus, special logic design was required for each applicationof the system, and a rewiring of the system logic was required for anychange in a system's multiple character sequences.

A problem similar to that described above also arises in applicationswhere the information is to be transmitted over lines. If frequentlyused character combinations could be transmitted as a single character,significant savings in transmission time and bandwidth would beobtained..I-Iowever, a capability must be provided for-converting thetransmitted characters into the desired multiple character sequence atthe receiving station. Again, flexibility in design and ease in makingalterations are desirable. I,

t It is, therefore, aprimary object of this invention to provide asimproved circuit for converting a single coded input character into aplurality of coded output characters.

A more specific object of this invention is to provide a circuit forgenerating a plurality .of output characters as a result of a single keydepression on a keyboard.

A still more specific object of this invention is to provide a circuitof the type indicated above which permits the output character sequencesto be easily modified.

A further object of this invention is to provide a circuit of the typeindicated above which provides flexibility over a wide range in thelength of the character sequences which may be obtained.

In accordance with these objects, this invention provides a circuit forconverting a single coded input character into a plurality of codedoutput characters. The circuit includes a character generator meansadapted to generate a predetermined coded output character in'responseto the application thereto of a selected combination of input bits. Acounter means is provided, with at least a portion of an input characterbeing applied as part of the inputto the character generator, and theoutput from the counter means being applied as the remaining input tothe character generator. Each time an out put is generated by thecharactergenerator, the output from the counter is altered. When apredetermined output is obtained from the character generator, thegenerating of new characters by the character means is terminated. Theforegoing and other objects, features and advantages of the inventionwill be apparent from the following more particular descrip tion ofpreferred embodiments of the invention as illustrated in theaccompanying drawings.

In the drawings: drawings.

In FIG. 1 is a schematic block diagram of an illustrative embodiment ofthe invention.

FIG. 2 is a schematic block diagram of an alternative embodiment of theinvention.

Referring now to FIG. 1, it is seen that an input code is derived onlines 10 from a keyboard 12. Forpurposes of the following discussion itwill be assumed that either the circuit operates quickly enough so thatthe multiple character generation can be completed during the minimumtime that a key is depressed, as would normally be the case, or that thekeyboard is of a locking variety in which a key is not released until arelease signal is received. Thus, signals remain on lines 10 until allrequired characters have been generated.

For the illustrated embodiment of the invention, it has been assumedthat there are seven lines 10 and that the coded output from keyboard 12is in the seven bit ASCII code. From the discussion to follow, it willbe apparent that, while in FIG. 1, a keyboard has been shown forapplying signals to lines 10, ASCII codes could be applied to theselines from some other source such as, for example a transmission line ora radio receiver. With such an input, a buffer register might berequired in order to hold the input code until the completion of themultiple-character generation operation.

Multiple-character (MC) flip-flop 14 is normally in its ZERO stategenerating an output signal on line 16 which isapplied to conditiongates 18 to pass on lines 10 through lines 20, OR gates 22, and lines 24to be stored in memory 26. Thus, as long as MC flip-flop 14 is in itsZERO state, input characters on lines 10 are stored directly in memory26. These characters may be stored in parallel, or may be serializedbefore being stored. Memory 26 may, for example, be standardrecirculatingdelay line, drum or disk.

However, when detector 28 generates an output on line 30, indicatingthat the character code on lines 10 is one of the special codes whichappears in column, or stick, 6, in ASCII code, MC flip-flop 14 is set toits ONE state. This deconditions gates 18, preventing the character online 10 from being stored in memory 26. As a practical matter, a shortdelay may be required in the circuit prior to gate 18 in order to permitthe detection operation in circuit 28, and the setting of flip-flop 14,to be completed before the character reaches this gate.

The four least significant, or row, lines of the lines 10 are connectedas four of the inputs to character generator 32. Generator 32 may be anyof a variety of known circuits which are capable of accepting codedinputs on a first selected number of lines and of generating, throughthe use of "matrix combinations of gates, diodes and/or the like, aunique output on a second selected number of lines. A read-only memorymight also be'utilized for the generator 32. While the particulargenerator utilized is not a critical part of the present invention, agenerator suitable for this purpose will be described later. Theremaining N inputs to the character generator matrix are the N outputlines 34 from counter 36. The number of lines 34, and therefore the sizeof the counter 36, depends on the maximum number of characters which isrequired in an output multiple character sequence. Thus, if N is three,no more than eight characters are obtainable in an output sequence.Generally, the number of characters obtainable will be equal to (2").

In operation, counter 36 is initially reset to a count of zero. Themanner in which this is accomplished will be described later. Thus, theinitial code applied to matrix 32 is the row code of the input characteron lines 10, plus all zeros on lines 34. This input code is converted,by known encoding techniques, into the seven bit ASCII code for thefirst character of the desired output. This character, appearing onlines 38 is applied as the information input to gates 40. Since MCflip-flop 14 is now in its ONE state, a signal appears on ONE-sideoutput line 42 partially conditioning AND gate 44. At character clocktime, a signal appears on enable line 46, fully conditioning AND gate 44to generate an output on line 48 which is applied to condition gate 40to pass the character code on lines 38 through lines 50, OR gates 22,and lines 24 to be stored in memory 26. The signal on line 46 may bederived from memory 26 when it is in a condition to receive a newcharacter. The first character of the desired multiplecharacter sequenceis in this manner obtained and stored.

The character on lines 38 is also applied to end-of-sequence detector52. Detector 52 may, for example, be an AND gate, the inputs to whichare selected such that it generates an output signal on end-of-sequenceline 54 only when the selected end-of-sequence code, such as all zeros,appears on lines 38. Line 54 is connected through inverter 56 and line58 to one input of AND gate 60. ONE-side output line 42 from MC flipflopI4 is a second input to this AND gate with enable line 46 being itsfinal input. Thus, if the character code which was stored in memory isnot the end-of-sequence code, AND gate 60 is fully conditioned togenerate an output signal on line 62, which signal is applied to stepcounter 36. This increments the value appearing on line 34. Matrix 32 isarranged so that the code appearing on the first four of the lines plusthe incremented value on lines 34 results in the ASCII code for thesecond desired character of the character sequence appearing on lines38.

The above sequence of operations is repeated with a new character of thedesired sequence being generated each time counter 36 is incremented. Itshould be noted that the same output character may be generated as aresult of several different inputs. Thus, for the word sell,".lthe codeof the letter 1" is generated both when an output of 2 is generated bythe counter and when 3 output of 3 is generated.

When the last of the characters which it is desired to generate has beenstored in memory 26, the next incrementing of counter 36 results inmatrix 32 generating the end-ofsequence code on lines 38. In a preferredembodiment of the invention, this is accomplished by providing no outputfrom generator 32 for the input code which appears after the lastcharacter of a desired sequence has been generated. The resultingall-zeros input to detector 52 causes a signal on line 54 which isapplied to reset counter 36 to a count of zero and to reset MC flip-flop14 to its ZERO state. If a locking keyboard is utilized, the signal ofline 54 may also be applied to release keyboard 12. The circuit is thusreset in preparation of the next input code. It should be noted that nomeans has been shown in the circuit for suppressing the storage of theend-of-sequence code in memory 26. If desired, this may be accomplishedby utilizing line 58 as an additional input to AND gate 44.

A circuit has thus been described which is capable of storing either asingle character or a plurality of characters in response to a singlecode input. The number of characters which appear in each sequence maybe varied over a wide range depending on the size of the counter 36utilized, and single character sequences are possible. It can also beseen that the multiple-character sequences generated may be changedmerely by changing character generator matrix 32. Since this matrix maybe formed on a single printed circuit card, changes in the charactersequences become a relatively simple matter. If an ROM charactergenerator is utilized, changes may be even more easily effected bymerely reprogramming the ROM.

For the illustrative embodiment of the invention, the characters storedin memory 26 are utilized to control the display on a cathode-ray tube(CRT) display device. Thus, the contents of memory 26 are appliedthrough line 64 to video code character generator 66. As will be seenshortly, this generator may be of the same general form as the generator32, thus simplifying design and reducing total system cost. The videocode output on line 68 from generator 66 is applied to control andrefresh the display on display device 70.

Since character generator 32 is the most expensive element of thecircuit in FIG. I, the cost of a system having multiple inputs may bereduced by having this element shared by a number of keyboards. FIG. 2shows such a multiplexed system and also shows in more detail a selectedembodiment for character generator matrix 32 and counter 36.

Referring now to FIG. 2 it is see that there are three keyboards l2A-l2Ceach of which is adapted to generate outputs in a selected code, such asASCII, on corresponding output lines 10. These outputs would normally beapplied through gates 18, such as that shown in FIG. '1, to be stored ina memory 26. The particular keyboard which has access to memory at anygiven time is determined by input assignment logic 76. This logicaccepts inputs from a system master clock (not shown) and generatesoutputs on one of three lines, designated C1, C2, C3, to indicate whichof the three input keyboards is to have access to the memory at a giventime.

When a column 6 character is detected in one of the keyboards 12, itgenerates an output on the corresponding line 78 to cause thecorresponding MC flip-flop of the MC flipfiops 14 to be set to its ONESTATE. This results in a signal on the corresponding one of the three MClines 42.

The four least significant bits, or row bits, of the code appearing on aset of lines 10 are applied to the appropriate gate of input assignmentlogic circuit 80. This circuit would consist of three sets of gates, onefor each of the sets of lines 10, with corresponding outputs from eachof the sets being ORed together. Each set of gates is conditioned by acorresponding one of the clocklines C1-C3. When a signal appears on theappropriate clock line, the signals on lines 10 are passed throughcircuit 80 and lines 82 to form one set of inputs to character generatormatrix 84.

Character generator matrix 84 is the same as the front end of thecharacter generator 66 (FIG. 1) used for converting ASCII code to videocode. This circuit accepts the seven-bit ASCII input and generates theequivalent 35-bit video output. These 35 bits on lines 86 are applied toa second character encoder 88 which gates these bits, seven bits at atime, to the display device under control of a stroke counter. Thus, theseven bits for the first stroke would be applied to the display deviceduring stroke one time, followed by the seven bits of the second strokeduring stroke two time, as so on until all five strokes of the five byseven character have been generated. A code generator of this generaltype is shown in U.S. Pat. No. 3,440,646 entitled CODE CONVERSION MEANSwhich issued to E. M. Dean on Apr. 22, 1969 and is assigned to theassignee of the instant application. The discussion to follow will showhow this character generator may be utilized as the character generatormatrix 32.

As was indicated previously, in addition to the 35 lines 86, matrix 88also has as inputs five lines 90 only one of which has a signal on it atany time. These lines would normally indicate the stroke of thecharacter which is being generated. However, in this invention, they aremerely used as additional code inputs. Thus, the circuit has threestroke substitute character counters (SSCCs) 92 each of which isnormally set to generate an output on the first of its five output lines94. The lines 94 are connected through a gating circuit designated SSCCselector 96 to the five lines 90. Thus at C1 time lines 94A will beconnected to the lines 90, at C2 time lines 94B will be connected, andat C1 time lines 94C will be connected.

Matrix 84 is adapted to receive seven inputs only four of which aresupplied by the lines 82. The remaining three inputs are output lines 98from sequence counter (SC) selector 100. Selector 100 is a gatingcircuit which connects one of the three sets of output lines 102 from asequence counter 104 to line 98 under control of the assignment logicclock lines. All of the sequence counters are initially set to zero.

While matrix 88 generates outputs on its seven output lines 105 at eachcharacter time, these outputs are not utilized until one of the MCflip-flops 14 is set to its ONE state. This results in a signal on oneof the lines 42 which is applied as an input to a corresponding AND gate106. The other inputs to each of the AND gates 106 are enable line 46and the corresponding assignment logic clock line, output lines 108 fromAND gates 106 are applied to gate the signals on generator matrix outputlines 105 to a memory (such as memory 76 shown in FIG. 1) and are alsoapplied as a step input to the corresponding SSCC. Thus, during thefirst character time that a signal appears on a line 42, the characterresulting from the input code on line 82, plus an all zero code on lines98, plus a signal on the first of the lines 90, is applied through lines105, loadmemory selector circuit 109, and line 111 to be stored inmemory. The appropriate SSCC is also incremented. During the nextcharacter time the character which results from the same combination ofinputs on lines, but from a signal on the second of the lines 90,appears on the circuit output line. The appropriate SSCC is againincremented. This process continues until the fifth character of thesequence is generated at which time the SSCC is incremented back to itsinitial condition and an overflow signal appears on the appropriate line110 causing the corresponding sequence counter to be incremented.Additional characters may now be generated, with a new input nowappearing on lines 98, as the appropriate SSCC is again stepped throughits five conditions. This sequence of operation may be repeated two moretimes until a count of three appears on lines 98. Thus, the circuit iscapable of generating five character codes as a result of the SSCCcounter for each of four possible outputs from the correspondingsequence counter for a total of 20'p0ssible characters.

After the generation of any character, the character sequence may beterminated by providing no code output for matrix 88 for the combinationof inputs applied to it on lines 86 and 90. The detection of this allzeros code results in an endmf-sequence signal on line 54 which isapplied to reset the appropriate MC flip-flop l4 and to reset the SSCCand SC counters. The circuit is thus reset in preparation for the nextinput, and, as with the general embodiment of the invention shown inFIG. 1, characters are again permitted to flow directly from keyboard tomemory.

While the invention has been particularly shown and described withreference to preferred -embodiments thereof, it will be understood bythose skilled in the art that the various changes in form and detailspreviously discussed, as well as others, may be made therein withoutdeparting from the spirit and scope of the invention. What is claimedis: 1. A circuit for converting a single coded input character into aplurality of coded output characters comprising:

character generator means adapted to generate a predetermined codedoutput character in response to the application thereto of a selectedcombination of input bits;

means for applying at least a portion of an input character as inputbits to said character generator means; counter means; means forapplying the output from said counter means as the remaining input bitsto said character generator means;

means operative only at times when an output character is be generatedby said character generator means for altering the output from saidcounter means; and

means responsive to a predetermined output from said character generatormeans for terminating the generating of characters by said charactergenerator means.

2. A circuit of the type described in claim 1 wherein the count in saidcounter means is incremented each time an output character is generated.

3. A circuit of the type described in claim 2 wherein there are aplurality of said counter means, wherein the count in a first of saidcounter means is incremented each time an output character is generated;and

wherein the counts in said remaining counter means are incremented eachtime an overflow occurs from the preceding counter means.

4. A circuit of the type described in claim 1 wherein said coded inputcharacter is derived from the depression of a single key on a keyboard.

5. A circuit of the type described in claim 1 including means forindicating that an input character may represent a plurality of outputcharacters; I

a character storage means;

means for normally passing input characters directly to said characterstorage means; and

means responsive to an output from said indicating means for applying aninput character to said converting circuit and for applying the outputfrom said converting circuit to said character storage means. 6. Acircuit of the type described in claim 5 wherein said input charactersare coded in ASCII; and

wherein said indicating means is energized when a character in aselected stick of said ASCII code is applied to said circuit.

7. A circuit of the type described in claim 1 wherein said charactergenerator means does not have a coded output which corresponds to thecoded input applied to said character generator after the last characterof a desired sequence has been generated whereby said predeterminedoutput is an all zeros code.

8. A circuit of the type described in claim 1 including a plurality ofdifferent sources for said coded input characters;

a separate counter means for each of said sources;

means for indicating the input character source which is to have accessto said character generator at any given time; and

means responsive to said indicating means for gating the outputs fromthe indicated source and its corresponding counter means to saidcharacter generator.

9. A circuit of the type described in claim 1 wherein said charactergenerator is in two parts;

wherein said counter means is in two parts;

wherein the first part of said character generator accepts the portionof the input character and the output from one of said counter means andgenerates as an output an intermediate code; and

wherein the second of said character generator means accepts saidintermediate code and the output from the other said counter means togenerate the desired coded output character.

10. A circuit of the type described in claim 9 wherein said secondcounter is a stroke substitute counter which is incremented after eachcharacter is generated and wherein said first counter means isincremented when an overflow occurs from said stroke substitute counter.

1. A circuit for converting a single coded input character into aplurality of coded output characters comprising: character generatormeans adapted to generate a predetermined coded output character inresponse to the application thereto of a selected combination of inputbits; means for applying at least a portion of an input character asinput bits to said character generator means; counter means; means forapplying the output from said counter means as the remaining input bitsto said character generator means; means operative only at times when anoutput character is be generated by said character generator means foraltering the output from said counter means; and means responsive to apredetermined output from said character generator means for terminatingthe generating of characters by said character generator means.
 2. Acircuit of the type described in claim 1 wherein the count in saidcounter means is incremented each time an output character is generated.3. A circuit of the type described in claim 2 wherein there are aplurality of said counter means, wherein the count in a first of saidcounter means is incremented each time an output character is generated;and wherein the counts in said remaining counter means are incrementedeach time an overflow occurs from the preceding counter means.
 4. Acircuit of the type described in claim 1 wherein said coded inputcharacter is derived from the depression of a single key on a keyboard.5. A circuit of the type described in claim 1 including means forindicating that an input character may represent a plurality of outputcharacters; a character storage means; means for normally passing inputcharacters directly to said character storage means; and meansresponsive to an output from said indicating means for applying an inputcharacter to said converting circuit and for applying the output fromsaid converting circuit to said character storage means.
 6. A circuit ofthe type described in claim 5 wherein said input characters are coded inASCII; and wherein said indicating means is energized when a characterin a selected stick of said ASCII code is applied to said circuit.
 7. Acircuit of the type described in claim 1 wherein said charactergenerator means does not have a coded output which corresponds to thecoded input applied to said character generator after the last characterof a desired sequence has been generated whereby said predeterminedoutput is an all zeros code.
 8. A circuit of the type described in claim1 including a plurality of different sources for said coded inputcharacters; a separate counter means for each of said sources; means forindicating the input character source which is to have access to saidcharacter generator at any given time; and means responsive to saidindicating means for gating the outputs from the indicated source andits corresponding counter means to said character generator.
 9. Acircuit of the type described in claim 1 wherein said charactergenerator is in two parts; wherein said counter means is in two parts;wherein the first part of said character generator accepts the portionof the input character and the output from one of said counter means andgenerates as an output an intermediate code; and wherein the second ofsaid character generator means accepts said intermediate code and theoutput from the other said counter means to generate the desired codedoutput character.
 10. A circuit of the type described in claim 9 whereinsaid second counter is a stroke substitute counter which is incrementedAfter each character is generated and wherein said first counter meansis incremented when an overflow occurs from said stroke substitutecounter.